Performance optimization of Carry Select Adders using Variable Latency design style

This paper presents a Variable Latency (VL) adder. It is introduced to work at a lower time delay than that required by a Ripple Carry Adder (RCA). It proposes a new technique called HOLD LOGIC. The VL-adder design is further modified to overcome the effects of negative bias temperature instability (NBTI). In the CLDC (Carry Length Detection Circuit), more number of components are used and it performs clock stretching. Here HOLD LOGIC circuit is used to reduce the number of components used in CLDC circuit. Because of the HOLD LOGIC, the delay, and the number of gates are reduced. Xilinx ISE is used for simulation and synthesis.